View AK4101VQ_6453816.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei [ak4101] ms0076-e-01 2001/12 - 1 - general description the ak4101 is a four outputs digital audio transmitter(dit) which supports data rate up to 192khz sample rate operation. the ak4101 encodes and transmits audio data according to the aes3, iec60958, s/pdif & eiaj cp1201 interface standards. the ak4101 accepts audio and digital data, which is then multiplexed, encoded and driven on to a cable. the audio serial port is double buffered and supports eight formats. features sampling rate up to 192khz support aes3, iec60958, s/pdif & eiaj cp1201 professional and consumer formats generates crc codes and parity bits four on-chip rs422 line drivers 64-byte on-chip buffer memory for channel status and user bits supports synchronous/asynchronous access to channel status and user bits supports multiple clock frequencies: 128fs, 256fs, 384fs and 512fs supports left/right justified and i 2 s audio formats easy to use 4 wire, serial host interface audio routing mode (transparent mode) power supply: 4.75 to 5.25v ttl level i/f small package: 44pin lqfp temperature range of -10 to 70 c quad outputs 192khz 24-bit dit ak4101
asahi kasei [ak4101] ms0076-e-01 2001/12 - 2 - block diagram host serial interface audio serial interface bick lrck sdti1 txp1 mux crc generator prescaler rs422 line drivers biphase encoder sdti2 sdti3 sdti4 dif2 di dif1 di dif0 di cks1 di cks0 mclk bls trans vss di vdd di txn1 txp2 txn2 txp3 txn3 txp4 txn4 c1 c2 c3 c4 u1 u2 u3 u4 v12 v34 fs0 fs1 fs2 fs3 register csn cclk cdti cdt o ans pdn
asahi kasei [ak4101] ms0076-e-01 2001/12 - 3 - ordering guide AK4101VQ -10 +70 c 44pin lqfp (0.8mm pitch) pin layout pdn trans 1 mclk 44 2 sdti1 3 sdti2 4 sdti3 5 sdti4 6 vdd 7 vss 8 bick 9 lrck 10 fs0/csn 11 v34 43 v12 42 41 40 u2 39 u1 38 dif2 3 7 dif1 36 vdd 35 dif0 34 fs1/cdti 12 fs2/cclk 13 fs3/cdto 14 c1 1 5 c2 16 1 7 c4 18 ans 19 bls 20 cks0 21 vss 22 33 32 31 30 29 28 27 26 25 24 23 txp1 txn1 txp2 txn2 vss vdd txp3 txn3 txp4 txn4 cks1 AK4101VQ top view c3 u4 u3
asahi kasei [ak4101] ms0076-e-01 2001/12 - 4 - pin/function no. pin name i/o description 1 pdn i power down & reset pin (pull-up pin) when ?l?, the ak4101 is powered-down, txp/n pins are ?l? and the control registers are reset to default values. 2 mclk i master clock input pin 3 sdti1 i audio serial data input 1 pin 4 sdti2 i audio serial data input 2 pin (pull-down pin) 5 sdti3 i audio serial data input 3 pin (pull-down pin) 6 sdti4 i audio serial data input 4 pin (pull-down pin) 7 vdd - power supply pin, 4.75v 5.25v 8 vss - ground pin, 0v 9 bick i/o audio serial data clock input/output pin serial clock for sdti pins which can be configured as an output based on the dif2-0 inputs. 10 lrck i/o input/output channel clock pin indicates left or right channel, and can be configured as an output based on the dif2-0 inputs. fs0 i sampling frequency select 0 pin at synchronous mode (pull-down pin) csn i host interface chip select pin at asynchronous mode (pull-down pin) 11 akmode i ak4112a mode pin at audio routing mode (pull-down pin) 0: non-akm receivers mode, 1: ak4112a mode fs1 i sampling frequency select 1 pin at synchronous mode (pull-down pin) 12 cdti i host interface data input pin at asynchronous mode (pull-down pin) fs2 i sampling frequency select 2 pin at synchronous mode (pull-down pin) 13 cclk i host interface bit clock input pin at asynchronous mode (pull-down pin) fs3 i sampling frequency select 3 pin at synchronous mode (pull-down pin) 14 cdto o host interface data output pin at asynchronous mode (pull-down pin) 15 c1 i channel status bit input pin for channel 1 16 c2 i channel status bit input pin for channel 2 (pull-down pin) 17 c3 i channel status bit input pin for channel 3 (pull-down pin) 18 c4 i channel status bit input pin for channel 4 (pull-down pin) 19 ans i asynchronous/synchronous mode select pin (pull-up pin) 0: asynchronous mode, 1: synchronous mode 20 bls i/o block start input/output pin (pull-down pin) in normal mode, the channel status block output is ?h? for the first four bytes. in audio routing mode, the pin is configured as an input. when pdn= ?l?, bls pin goes ?h? at normal mode. 21 cks0 i clock mode select 0 pin (pull-up pin) 22 vss - ground pin, 0v
asahi kasei [ak4101] ms0076-e-01 2001/12 - 5 - no. pin name i/o description 23 cks1 i clock mode select 1 pin (pull-down pin) 24 txn4 o negative differential output pin for channel 4 25 txp4 o positive differential output pin for channel 4 26 txn3 o negative differential output pin for channel 3 27 txp3 o positive differential output pin for channel 3 28 vdd - power supply pin, 4.75v 5.25v 29 vss - ground pin, 0v 30 txn2 o negative differential output pin for channel 2 31 txp2 o positive differential output pin for channel 2 32 txn1 o negative differential output pin for channel 1 33 txp1 o positive differential output pin for channel 1 34 dif0 i audio serial interface select 0 pin (pull-down pin) 35 vdd - power supply pin, 4.75v 5.25v 36 dif1 i audio serial interface select 1 pin (pull-down pin) 37 dif2 i audio serial interface select 2 pin (pull-down pin) 38 u1 i user data bit input pin for channel 1 (pull-down pin) 39 u2 i user data bit input pin for channel 2 (pull-down pin) 40 u3 i user data bit input pin for channel 3 (pull-down pin) 41 u4 i user data bit input pin for channel 4 (pull-down pin) 42 v12 i validity bit input pin for channel 1 & channel 2 43 v34 i validity bit input pin for channel 3 & channel 4 (pull-down pin) 44 trans i audio routing mode (transparent mode) pin at synchronous mode 0: normal mode, 1: audio routing mode (transparent mode) notes: 1. internal pull-up and pull-down resistors are connected on-chip. the value of the resistors is 43k ? (typ). 2. all input pins except internal pull-down/pull-up pins should not be left floating.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 6 - absolute maximum ratings (vss=0v; note 3) parameter symbol min max units power supply vdd -0.3 6.0 v input current (all pins except supply pins) iin - 10 ma input voltage vin -0.3 vdd+0.3 v ambient operating temperature ta -10 70 c storage temperature tstg -65 150 c notes: 3. all voltages with respect to ground. warning: operation at or beyond these limits may results in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v; note 1) parameter symbol min typ max units power supply vdd 4.75 5.0 5.25 v *akm assumes no responsibility for the usage beyond the conditions in this datasheet. dc characteristics (ta=25 c; vdd=4.75~5.25v) parameter symbol min typ max units power supply current (fs=108khz, note 4) idd 10 20 ma high-level input voltage low-level input voltage vih vil 2.4 - - - - 0.8 v v high-level output voltage (except txp/n pins: iout=-400a) (txp/n pins: iout= -8ma) low-level output voltage (except txp/n pins: iout= 400a) (txp/n pins: iout= 8ma) voh voh vol vol vdd-1.0 vdd-0.8 - - - - - - - - 0.4 0.6 v v v v input leakage current iin - - 10 a notes: 4. power supply current (idd) is 4ma(typ)@fs=48khz and 12ma(typ)@fs=192khz. idd increases by 20ma(typ) per channel with professional output driver circuit. idd is 90ma(typ) if all four channels have professional output driver circuit. idd is 150a(typ) if pdn= ?l?, trans= ?h? and all other input pins except internal pull-up/pull-down pins are held to vss.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 7 - switching characteristics (ta=25 c; vdd=4.75~5.25v; c l =20pf) parameter symbol min typ max units master clock timing frequency duty cycle fclk dclk 3.584 40 27.648 60 mhz % lrck timing frequency duty cycle at slave mode duty cycle at master mode fs dlck 28 45 50 192 55 khz % % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 5) bick ? ? to lrck edge (note 5) sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tsdh tsds 36 15 15 15 15 8 8 ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck sdti hold time sdti setup time fbck dbck tmblr tsdh tsds -20 20 20 64fs 50 20 hz % ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z (note 6) tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 520 50 50 45 70 ns ns ns ns ns ns ns ns ns ns power-down & reset timing pdn pulse width tpdw 150 ns notes: 5. bick rising edge must not occur at the same time as lrck edge. 6. cdto pin is internally connected to a pull-down resistor.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 8 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk = tclkh x fclk x 100 = tclkl x fclk x 100 vih lrck vil 1/fs tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr audio interface timing (slave mode) lrck bick tmblr 50%vdd 50%vdd sdti tsdh tsds vih vil audio interface timing (master mode)
asahi kasei [ak4101] ms0076-e-01 2001/12 - 9 - tcckl csn cclk tcds cdti tcdh tcss c0 * tcckh cdto hi-z (with pull-down resistor) * c1 vih vil vih vil vih vil write/read command input timing tcsw csn cclk cdti d2 d0 tcsh cdto d1 d3 vih vil vih vil vih vil hi-z (with pull-down resistor) write data input timing csn cclk tdcd cdto cdti a1 a0 hi-z (with pull-down resistor) 50%vdd vih vil vih vil vih vil d7 d6 d5 read data output timing 1
asahi kasei [ak4101] ms0076-e-01 2001/12 - 10 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%vdd vih vil vih vil vih vil read data output timing 2 tpdw pdn vil power-down & reset timing
asahi kasei [ak4101] ms0076-e-01 2001/12 - 11 - operation overview general description the ak4101 is a monolithic cmos circuit that encodes and transmits audio and digital data according to the aes3, iec60958, s/pdif and eiaj cp1201 interface standards. there are four sets of stereo channels that can be transmitted simultaneously. the chip accepts audio data and control data separately, multiplexes and biphase-mark encodes the data internally, and drives it directly or through a transformer to a transmission line. there are two modes of operation: asynchronous and synchronous. the asynchronous mode is fully software programmable through a serial control interface and contains buffer memory for control data. the synchronous mode has dedicated pins for the important control bits and a serial input port for the c, u and v bits. initialization the ak4101 takes 8 bit clock cycles to initialize after pdn goes inactive. also, for correct synchronization, mclk should be synchronized with lrck but the phase is not critical. an internal reset will occur if the relationship between mclk and lrck shifts by 3 mclk cycles from their initial conditions. mclk and lrck relationship for correct synchronization, mclk and lrck should be derived from the same clock signal either directly (as through a frequency divider) or indirectly (for example, as through a dsp). the relationship of bick to lrck is fixed and should not change. if mclk or lrck move such that they are shifted 3 or more mclk cycles from their initial conditions, the chip will generate an internal reset. after this reset, the tx outputs will transmit default values. the following frequencies are supported for mclk: 128fs/256fs/384fs/512fs. cks1 cks0 mclk fs 0 0 128fs 28k-192khz 0 1 256fs 28k-108khz 1 0 384fs 28k-54khz 1 1 512fs 28k-54khz table 1. mclk frequency asynchronous mode/ synchronous mode 1. asynchronous mode (software controlled) the ak4101 can be configured in the asynchronous mode by connecting the ans pin to logic ?l?. in this mode the 16 to 24-bit audio samples are accepted through a configured audio serial port, and the channel status and user data through a serial control host interface (sci). the sci allows access to internal buffer memory and control registers which are used to store the channel status and user data. 4bytes per channel of user and channel status is stored. this data is multiplexed with the audio data from the audio serial port, the parity bit is generated, and the bit stream is biphase-mark encoded and driven through the rs422 line drivers. the crcc code for the channel status is also generated according to the professional mode definition in the aes3 standards. this mode also allows for software control for mute, reset, audio format selection, clock frequency settings and output enables, via the serial host interface.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 12 - 2. synchronous mode (hardware controlled) the ak4101 when configured in synchronous mode accepts 16 - 24 bit audio samples through the audio serial port and provides dedicated pins for the control data and allows all channel status, user data and validity bits to be serially input through port pins. this data is multiplexed, the parity bit generated, and the bit stream is biphase-mark encoded and driven through an rs422 line driver. the four set of channels have individual channel status and user data pins. 2-1. audio routing mode (transparent mode) the ak4101 can be configured in audio routing mode (transparent mode) by ans=trans=1. in this mode, the channel status(c), user data(u) and validity(v) bits must pass through unaltered. the block start(b) signal is configured as an input, allowing the transmit block structure to be slaved to the block structure of the receiver. the c, u and v are now transmitted with the current audio sample. in audio routing mode, no crc bytes are generated and c bits pass through unaltered. in audio routing mode, the fs0/csn pin changes definition to akmode pin. when set ?h? the ak4101 can be configured directly with the ak4112a receiver. when set ?l?, it may be used with other non-akm receivers. setting the part with trans=1 and ans=0 is illegal and places the chip into a test mode. pin modes ans trans synchronous/asynchronous audio routing source for c, u and v bits 0 0 asynchronous mode normal mode c pin ored control register u pin ored control register v pin ored control register 0 1 (test mode) 1 0 normal mode 1 1 synchronous mode audio routing mode c,u and v pin table 2. mode setting bls c (or u,v) c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) sdti lrck (i 2 s) l0 r0 l31 r31 r191 l1 l32 lrck (except i 2 s) figure 1. audio routing mode timing (akmode=0)
asahi kasei [ak4101] ms0076-e-01 2001/12 - 13 - bls c (or u,v) lrck c(l0) c(r0) c(l1) c(r31) c(l31) c(l32) c(r191) sdti (except i 2 s) l191 r191 l0 r30 r31 l31 sdti (i 2 s) l191 r191 l30 l31 r30 l0 r190 r0 figure 2. audio routing mode timing (akmode=1) block start timing normal mode in normal mode (trans=0), the block start signal is an output. it goes ?h? two bit cycle after the beginning of b channel of frame 0 in each block, and stays ?h? for the first 32 frames. audio routing mode (transparent mode) in audio routing mode (transparent mode) (ans=trans=1), the block start becomes an input. except in i 2 s mode, a block start signal sampled any time from the first positive bick edge of the previous left channel to the positive bick edge preceding the transition of an lrck indicating the left channel will result in the current left channel being taken as the first sub frame of the current block. see figure 3 below. bick lrck (except i 2 s) left sub-frame a left sub-frame b lrck (i 2 s) left sub-frame a left sub-frame b figure 3. block start timing in audio routing mode a block start signal arriving in the time frame shown will result in the usage of "left sub-frame b" as the first sub-frame of the block.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 14 - c, u, v serial ports normal mode in normal mode (trans=0), the cuv bits are captured (either from the pins, in synchronous mode, or the control registers, in the asynchronous mode) in the sub frame following the audio data. the v bit is set to zero to indicate the audio data is suitable for conversion. the v12 pin indicates validity for channels 1 & 2 and v34 pin indicates validity for channels 3 & 4 respectively. see figure 4 and figure 5. audio routing mode (transparent mode) in audio routing mode (transparent mode) (ans=trans=1), the cuv bits are captured with the same sub-frame as the data to which the cuv bits correspond. in all dif modes except 5 and 7, the cuv bits are captured at the first, rising edge of bick after an lrck transition. in modes 5 and 7 (i 2 s), the cuv bits are captured at the second rising edge. see figure 6 and figure 7. cuv bick lrck previous cuv frame a frame b frame a cuv figure 4. normal, dif modes 0, 1, 2, 3, 4, and 6 cuv bick lrck previous cuv frame a frame b frame a cuv figure 5. normal, dif modes 5 and 7 (i 2 s) cuv bick lrck frame a cuv frame a frame b frame b cuv figure 6. audio routing, dif modes 0, 1, 2, 3, 4, and 6 cuv bick lrck frame a cuv frame a frame b frame b cuv figure 7. audio routing, dif modes 5 and 7 (i 2 s)
asahi kasei [ak4101] ms0076-e-01 2001/12 - 15 - audio serial interface the audio serial interface is used to input audio data and consists of six pins: bit clock (bick), word clock (lrck) & four data pins (sdti 1-4). bick clocks in sdti, which is doubled buffered, while lrck indicates the particular channel, left or right. the dif 2-0 pins in synchronous mode and control registers in asynchronous mode select the particular input mode. 16-24 bits are supported in the right justified and left justified modes. the i 2 s mode is also supported. the ak4101 can be configured in master and slave modes. mode dif2 dif1 dif0 sdti lrck bick 0 0 0 0 16bit, right justified h/l (i) 32fs-128fs (i) 1 0 0 1 18bit, right justified h/l (i) 36fs-128fs (i) 2 0 1 0 20bit, right justified h/l (i) 40fs-128fs (i) 3 0 1 1 24bit, right justified h/l (i) 48fs-128fs (i) 4 1 0 0 24bit, left justified h/l (i) 48fs-128fs (i) 5 1 0 1 24bit, i 2 s l/h (i) 50fs-128fs (i) 6 1 1 0 24bit, left justified master mode h/l (o) 64fs (o) 7 1 1 1 24bit, i 2 s master mode l/h (o) 64fs (o) table 3. audio data format modes lrck(i) bick(i) sdti(i) 012 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 010 1 30 15 14 14 15 30 figure 8. mode 0 timing lrck(i) bick(i) sdti(i) 01 8 31 0 1 23:msb, 0:lsb lch data rch data 911 10 9 31 0 1 8 11 10 010 1 30 21 20 20 21 30 22 23 22 23 figure 9. mode 3 timing
asahi kasei [ak4101] ms0076-e-01 2001/12 - 16 - lrck bick sdti(i) 012 31 0 1 23:msb, 0:lsb lch data rch data 21 23 22 21 31 0 1 2 23 22 23 22 2 30 1 0 0 1 30 21 22 23 21 2 23 22 figure 10. mode 4, 6 timing mode 4: lrck, bick: input mode 6: lrck, bick: output lrck bick sdti(i) 012 31 0 1 23:msb, 0:lsb lch data rch data 23 32 31 0 1 23 3 23 22 24 1 0 24 32 23 22 2 0 1 21 22 23 22 figure 11. mode 5, 7 timing mode 5: lrck, bick: input mode 7: lrck, bick: output
asahi kasei [ak4101] ms0076-e-01 2001/12 - 17 - sampling frequency setting bits 3-0 of channel status byte 3 in consumer mode can be set by fs3-0 pins. also bits 7-6 of channel status byte 0 and bits 6-3 of channel status byte 4 in professional mode can be set by fs3-0 pins. fs[3:0] fs byte 3 bits 3-0 0000 44.1khz 0000 0001 reserved 0001 0010 48khz 0010 0011 32khz 0011 0100 reserved 0100 0101 reserved 0101 0110 reserved 0110 0111 reserved 0111 1000 reserved 1000 1001 reserved 1001 1010 reserved 1010 1011 reserved 1011 1100 reserved 1100 1101 reserved 1101 1110 reserved 1110 1111 reserved 1111 table 4. sampling frequency setting (consumer mode) fs[3:0] fs byte 0 bits 7-6 byte 4 bits 6-3 0000 not defined 00 0000 0001 44.1khz 01 0000 0010 48khz 10 0000 0011 32khz 11 0000 0100 not defined 00 0000 0101 not defined 00 0000 0110 not defined 00 0000 0111 not defined 00 0000 1000 for vectoring 00 1000 1001 22.05khz 00 1001 1010 88.2khz 00 1010 1011 176.4khz 00 1011 1100 192khz 00 0011 1101 24khz 00 0001 1110 96khz 00 0010 1111 not defined 00 1111 table 5. sampling frequency setting (professional mode)
asahi kasei [ak4101] ms0076-e-01 2001/12 - 18 - data transmission format data transmitted on the tx outputs is formatted in blocks as shown in figure 12. each block consists of 192 frames. a frame of data contains two sub-frames. a sub-frame consists of 32 bits of information. each data bit received is coded using a bi-phase mark encoding as a two binary state symbol. the preambles violate bi-phase encoding so they may be differentiated from data. in bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. for a logic 0, the second state of the symbol is the same as the first state. for a 1, the second state is the opposite of the first. figure 13 illustrates a sample stream of 8 data bits encoded in 16 symbol states. frame 191 frame 0 frame 1 sub-frame sub-frame m channel 1 w channel 2 b channel 1 w channel 2 m channel 1 w channel 2 figure 12. block format 0 1 1 0 0 0 1 0 figure 13. a biphase-encoded bit stream the sub-frame is defined in figure 14 below. bits 0-3 of the sub-frame represent a preamble for synchronization. there are three preambles. the block preamble, b, is contained in the first sub-frame of frame 0. the channel 1 preamble, m, is contained in the first sub-frame of all other frames. the channel 2 preamble, w, is contained in all of the second sub- frames. table 6 below defines the symbol encoding for each of the preambles. bits 4-27 of the sub-frame contain the 24 bit audio sample in 2?s complement format with bit 27 as the most significant bit. for 16 bit mode, bits 4-11 are all 0. bit 28 is the validity flag. this is ?h? if the audio sample is unreliable. bit 29 is a user data bit. frame 0 contains the first bit of a 192 bit user data word. frame 191 contains the last bit of the user data word. bit 30 is a channel status bit. again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. bit 31 is an even parity bit for bits 4-31 of the sub-frame. sync p c u v l m s audio sample s b b 0 3 4 27 28 29 30 31 figure 14. sub-frame format the block of data contains consecutive frames transmitted at a state-bit rate of 64 times the sample frequency, fs. for stereophonic audio, the left or a channel data is in channel 1 while the right or b data is in channel 2. for monophonic audio, channel 1 contains the audio data. preamble preceding state = 0 preceding state = 1 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 table 6. sub-frame preamble encoding
asahi kasei [ak4101] ms0076-e-01 2001/12 - 19 - line drivers there are four rs422 line drivers on chip. the aes3 specification states that the line driver shall have a balanced output with an internal impedance of 110 ohms 20% and also requires a balanced output drive capability of 2 to 7 volts peak-to-peak into 110 ohm load. the internal impedance of the rs422 driver along with a series resistors of 56 ohms realizes this requirement. for consumer use(s/pdif), the specifications require an output impedance of 75 ohms 20% and a driver level of 0.5 20% volts peak to peak. a combination of 330 ohms in parallel with 100 ohms realizes this requirement. the outputs can be set to ground by resetting the device or a software mute. txp txn 56 0.1u xlr connector transformer figure 15. professional output driver circuit txp txn 330 0.1u rca phono connector transformer 100 figure 16. consumer output driver circuit
asahi kasei [ak4101] ms0076-e-01 2001/12 - 20 - serial control interface in asynchronous mode, four of the dual function pins become csn, cclk, cdti and cdto, a 4 wire microprocessor interface. the internal 66 byte control register can then be read and written. the contents of the control register define, in part, the mode of operation for the ak4101. figure 17 illustrates the serial data flow associated with sci read and write operations. c1-0 is the chip address. the ak4101 looks for c1-0 to be a ?11? before responding to the incoming data. r/w is the read/write bit which is ?l? for a read operation and ?h? for a write operation. the register address contained in a7-0 is decoded to select a particular byte of the control register. d7-0 on cdti is the control data coming from the microprocessor during a write operation. d7-0 on cdto is the contents of the addressed byte from the control register requested during a read operation. the address and data bits are framed by csn=0. during a write operation, each address and data bit is sampled on the rising edge of cclk. during a read operation, the address bits are sampled on the rising edge of cclk while data on cdto is output on the falling edge of cclk. cclk has a maximum frequency of 5 mhz. cdti cclk csn c1 0 1 2 3 4 5 6 7 16 17 18 19 20 21 22 23 d4 d5 d6 d7 * * * * * c0 r/w d0 d1 d2 d3 cdto hi-z (with pull-down resistor) write cdti c1 d4 d5 d6 d7 * * * * * c0 r/w d0 d1 d2 d3 cdto hi-z (with pull-down resistor) read d4 d5 d6 d7 d0 d1 d2 d3 hi-z a7 8 9 10 11 12 13 14 15 a1 a2 a3 a4 a5 a6 a0 a7 a1 a2 a3 a4 a5 a6 a0 ?l? c1-c0: chip address (fixed to ?11?) r/w: read/write (0:read, 1:write) *: don?t care a7-a0: register address d7-d0: control data figure 17. control i/f timing csn ak4101 cclk cdti cdto csn ak4101 cclk cdti cdto p csn1 cclk cdti cdto csn2 figure 18. typical connection with p note: external pull-up resistor should not be attached to cdto pins since cdto pin is internally connected to the pull-down resistor.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 21 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clock/format control crce dif2 dif1 dif0 cks1 cks0 muten rstn 01h validity/fs control v4 v3 v2 v1 fs3 fs2 fs1 fs0 02h ch 1 a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 03h ch 1 a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 04h ch 1 a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 05h ch 1 a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 06h- 09h ch 1 b-channel c-bit buffer for byte 0-3 cb7 ? cb31 ? ? ? ? ? ? ? ? ? ? ? ? cb0 ? cb24 0ah- 0dh ch 1 a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 0eh- 11h ch 1 b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 12h- 15h ch 2 a-channel c-bit buffer for byte 0-3 ? 16h- 19h ch 2 b-channel c-bit buffer for byte 0-3 ? 1ah- 1dh ch 2 a-channel u-bit buffer for byte 0-3 ? 1eh- 21h ch 2 b-channel u-bit buffer for byte 0-3 ? 22h- 25h ch 3 a-channel c-bit buffer for byte 0-3 ? 26h- 29h ch 3 b-channel c-bit buffer for byte 0-3 ? 2ah- 2dh ch 3 a-channel u-bit buffer for byte 0-3 ? 2eh- 31h ch 3 b-channel u-bit buffer for byte 0-3 ? 32h- 35h ch 4 a-channel c-bit buffer for byte 0-3 ? 36h- 39h ch 4 b-channel c-bit buffer for byte 0-3 ? 3ah- 3dh ch 4 a-channel u-bit buffer for byte 0-3 ? 3eh- 41h ch 4 b-channel u-bit buffer for byte 0-3 ? table 7. register map notes: (1) in stereo mode, a indicates left channel and b indicates right channel. (2) in asynchronous mode, the dif2-0 and cks1-0 bits are logically ?ored? with the dif2-0 and cks1-0 pins. (3) for addresses from 42h to ffh, data is not written.
asahi kasei [ak4101] ms0076-e-01 2001/12 - 22 - register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h clock/format control crce dif2 dif1 dif0 cks1 cks0 muten rstn r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 0 1 1 rstn: timing reset. 0: resets the internal frame and bit counters. control registers are not initialized. txp pin is ?h? and txn pin is ?l?. in normal mode, bls pin is ?h?. 1: normal operation. (default) muten: power down and mute for asynchronous mode. 0: power down command. control registers are not initialized. txp and txn pins are ?l?. in normal mode, bls pin is ?h?. 1: normal operation. (default) cks1-0: master clock frequency select. (see table 1.) default: ?00? (mode 0: mclk=128fs) cks1-0 bits are logically ored with cks1-0 pins. dif2-0: audio data format. (see table 3.) default: ?000? (mode 0: 16bit right justified) dif2-0 bits are logically ored with dif2-0 pins. crce: crc enable at professional mode. 0: crc is not generated. 1: crc is generated at professional mode. in consumer mode, crc is not generated. (default) addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h validity/fs control v4 v3 v2 v1 fs3 fs2 fs1 fs0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 fs3-0: sampling frequency select. (see table 4 and table 5.) default: ?0000? (?44.1khz? in consumer mode; ?not defined? in professional mode. ) v1-4: validity flag for each channel. 0: valid (default) 1: invalid v12 pin v1 bit v2 bit v bit on tx1 v bit on tx2 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 table 8. v bit setting at asynchronous mode
asahi kasei [ak4101] ms0076-e-01 2001/12 - 23 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h ch 1 a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 06h ch 1 b-channel c-bit buffer for byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 12h ch 2 a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 16h ch 2 b-channel c-bit buffer for byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 22h ch 3 a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 26h ch 3 b-channel c-bit buffer for byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 32h ch 4 a-channel c-bit buffer for byte 0 ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 36h ch 4 b-channel c-bit buffer for byte 0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 1 0 0 c0-7: channel status byte 0 default: ?00100000? addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h ch 1 a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 07h ch 1 b-channel c-bit buffer for byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 13h ch 2 a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 17h ch 2 b-channel c-bit buffer for byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 23h ch 3 a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 27h ch 3 b-channel c-bit buffer for byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 33h ch 4 a-channel c-bit buffer for byte 1 ca15 ca14 ca13 ca12 ca11 ca10 ca9 ca8 37h ch 4 b-channel c-bit buffer for byte 1 cb15 cb14 cb13 cb12 cb11 cb10 cb9 cb8 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 c8-15: channel status byte 1 default: ?00000000?
asahi kasei [ak4101] ms0076-e-01 2001/12 - 24 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h ch 1 a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 14h ch 2 a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 24h ch 3 a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 34h ch 4 a-channel c-bit buffer for byte 2 ca23 ca22 ca21 ca20 ca19 ca18 ca17 ca16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 1 0 0 0 0 ca16-23: channel status byte 2 for a-channel default: ?00001000? addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h ch 1 b-channel c-bit buffer for byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 18h ch 2 b-channel c-bit buffer for byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 28h ch 3 b-channel c-bit buffer for byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 38h ch 4 b-channel c-bit buffer for byte 2 cb23 cb22 cb21 cb20 cb19 cb18 cb17 cb16 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 0 0 0 0 0 cb16-23: channel status byte 2 for b-channel default: ?00000100? addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h ch 1 a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 09h ch 1 b-channel c-bit buffer for byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 15h ch 2 a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 19h ch 2 b-channel c-bit buffer for byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 25h ch 3 a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 29h ch 3 b-channel c-bit buffer for byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 35h ch 4 a-channel c-bit buffer for byte 3 ca31 ca30 ca29 ca28 ca27 ca26 ca25 ca24 39h ch 4 b-channel c-bit buffer for byte 3 cb31 cb30 cb29 cb28 cb27 cb26 cb25 cb24 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 c24-31: channel status byte 3 default: ?01000000?
asahi kasei [ak4101] ms0076-e-01 2001/12 - 25 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 0ah- 0dh ch 1 a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 0eh- 11h ch 1 b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 1ah- 1dh ch 2 a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 1eh- 21h ch 2 b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 2ah- 2dh ch 3 a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 2eh- 31h ch 3 b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 3ah- 3dh ch 4 a-channel u-bit buffer for byte 0-3 ua7 ? ua31 ? ? ? ? ? ? ? ? ? ? ? ? ua0 ? ua24 3eh- 41h ch 4 b-channel u-bit buffer for byte 0-3 ub7 ? ub31 ? ? ? ? ? ? ? ? ? ? ? ? ub0 ? ub24 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 u0-31: user data default: all ?0?
asahi kasei [ak4101] ms0076-e-01 2001/12 - 26 - default values of control registers bits default crce 1 crc is generated. dif2-0 000 16bit, right justified cks1-0 00 mclk=128fs v4-1 0000 valid data fs3-0 0000 fs=44.1khz muten 1 normal operation rstn 1 normal operation channel status - bit0 0 consumer mode - bit1 0 audio mode - bit2 1 no copyright - bit3-5 000 no emphasis byte0 - bit6-7 00 mode 0 byte1 - bit0-7 00000000 general category code - bit0-3 0000 source number: don?t care byte2 - bit4-7 1000 0100 channel a source channel channel b source channel - bit0-3 0100 fs=48khz - bit4-5 00 standard clock accuracy byte3 - bit6-7 00 user data all zeros table 9. default values of control register
asahi kasei [ak4101] ms0076-e-01 2001/12 - 27 - package 0.15 0.17 0.05 0.37 0.10 10.00 1.70max 111 23 33 44 p in lqfp ( unit: mm ) 10.00 12.80 0.30 34 44 0.80 22 12 12.80 0.30 0 0.2 0 ? 10 0.60 0.20 package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
asahi kasei [ak4101] ms0076-e-01 2001/12 - 28 - marking AK4101VQ xxxxxxx japan 1 1) pin #1 indication 2) date code: xxxxxxx(7 digits) 3) marking code: AK4101VQ 4) country of origin 5) asahi kasei logo important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4101VQ

	To Download AK4101VQ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .